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authorJim Lawson2016-10-06 08:57:10 -0700
committerJim Lawson2016-10-06 08:57:10 -0700
commit82625071405672eb4a19363d6f73f359ac28a7f5 (patch)
treedee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/test/scala/chiselTests/Tbl.scala
parentb7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff)
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/Tbl.scala')
-rw-r--r--src/test/scala/chiselTests/Tbl.scala22
1 files changed, 12 insertions, 10 deletions
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index c79eb8a4..66a06435 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -2,20 +2,22 @@
package chiselTests
-import Chisel._
import org.scalatest._
import org.scalatest.prop._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
class Tbl(w: Int, n: Int) extends Module {
- val io = new Bundle {
- val wi = UInt(INPUT, log2Up(n))
- val ri = UInt(INPUT, log2Up(n))
- val we = Bool(INPUT)
- val d = UInt(INPUT, w)
- val o = UInt(OUTPUT, w)
- }
- val m = Mem(n, UInt(width = w))
+ val io = IO(new Bundle {
+ val wi = Input(UInt.width(log2Up(n)))
+ val ri = Input(UInt.width(log2Up(n)))
+ val we = Input(Bool())
+ val d = Input(UInt.width(w))
+ val o = Output(UInt.width(w))
+ })
+ val m = Mem(n, UInt.width(w))
io.o := m(io.ri)
when (io.we) {
m(io.wi) := io.d