cleanup

1 files changed, 0 insertions, 53 deletions

diff --git a/src/test/scala/chiselTests/SwitchSpec.scala b/src/test/scala/chiselTests/SwitchSpec.scala
deleted file mode 100644
index 52f50a53..00000000
--- a/src/test/scala/chiselTests/SwitchSpec.scala
+++ /dev/null
@@ -1,53 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests
-
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.util.{is, switch}
-
-class SwitchSpec extends ChiselFlatSpec with Utils {
-  "switch" should "require literal conditions" in {
-    a[java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
-      ChiselStage.elaborate(new Module {
-        val io = IO(new Bundle {})
-        val state = RegInit(0.U)
-        val wire = WireDefault(0.U)
-        switch(state) {
-          is(wire) { state := 1.U }
-        }
-      })
-    }
-  }
-  it should "require mutually exclusive conditions" in {
-    a[java.lang.IllegalArgumentException] should be thrownBy extractCause[IllegalArgumentException] {
-      ChiselStage.elaborate(new Module {
-        val io = IO(new Bundle {})
-        val state = RegInit(0.U)
-        switch(state) {
-          is(0.U) { state := 1.U }
-          is(1.U) { state := 2.U }
-          is(0.U) { state := 3.U }
-        }
-      })
-    }
-  }
-  it should "provide useful source locators" in {
-    val chirrtl = ChiselStage.emitChirrtl(new Module {
-      val io = IO(new Bundle {
-        val in = Input(UInt(2.W))
-        val out = Output(UInt(2.W))
-      })
-
-      io.out := 0.U
-      switch(io.in) {
-        is(0.U) { io.out := 3.U }
-        is(1.U) { io.out := 0.U }
-        is(2.U) { io.out := 1.U }
-        is(3.U) { io.out := 3.U }
-      }
-    })
-
-    (chirrtl should not).include("Conditional.scala")
-  }
-}