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| author | Jim Lawson | 2016-04-26 13:37:39 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-04-26 13:37:39 -0700 |
| commit | 6183533596a1706c65cb20d07a9d42eadac32df2 (patch) | |
| tree | 18a215bf0b19b50d8de8cbaa815f9918d4c7b0b8 /src/test/scala/chiselTests/Stack.scala | |
| parent | 09958f63470697188e1ed1a01c7ea39b8c56e7ef (diff) | |
Replace deprecated usage in tests. Issue #149
Diffstat (limited to 'src/test/scala/chiselTests/Stack.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Stack.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 600934aa..ac799c8a 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -13,7 +13,7 @@ class ChiselStack(val depth: Int) extends Module { val dataOut = UInt(OUTPUT, 32) } - val stack_mem = Mem(UInt(width = 32), depth) + val stack_mem = Mem(depth, UInt(width = 32)) val sp = Reg(init = UInt(0, width = log2Up(depth + 1))) val out = Reg(init = UInt(0, width = 32)) |