Merge branch 'master' into tobits-deprecation

1 files changed, 14 insertions, 10 deletions

diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index f2620d88..a9086223 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -3,8 +3,9 @@
 package chiselTests
 
 import org.scalatest._
-import Chisel._
-import Chisel.testers.BasicTester
+import chisel3._
+import chisel3.core.DataMirror
+import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
@@ -15,20 +16,23 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=UInt(width=3), init=UInt(20))
-      reg.width.get should be (2)
+      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
   }
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=UInt(width=3), init=UInt(20))
-      reg1.width.known should be (false)
+      val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20))
+      reg1.isWidthKnown should be (false)
+      DataMirror.widthOf(reg1).known should be (false)
       val reg2 = Reg(init=UInt(20))
-      reg2.width.known should be (false)
-      val reg3 = Reg(next=UInt(width=3), init=UInt(width=5))
-      reg3.width.known should be (false)
+      reg2.isWidthKnown should be (false)
+      DataMirror.widthOf(reg2).known should be (false)
+      val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5))
+      reg3.isWidthKnown should be (false)
+      DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
   }
@@ -36,7 +40,7 @@ class RegSpec extends ChiselFlatSpec {
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
       val reg2 = Reg(init=UInt(20, width=7))
-      reg2.width.get should be (7)
+      reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }
   }