diff options
| author | Albert Magyar | 2020-07-21 17:40:16 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-21 17:40:16 -0700 |
| commit | 473a13877c60ba9fb13de47542a8397412c2b967 (patch) | |
| tree | 159cec6aa6ece2e87ceffbdc56a553fe71d0726b /src/test/scala/chiselTests/PrintableSpec.scala | |
| parent | 4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff) | |
| parent | e5568f55a6a149adfd19ad04b264a69078288f86 (diff) | |
Merge pull request #1519 from freechipsproject/no-scalastyle
Remove scalastyle configurations
Diffstat (limited to 'src/test/scala/chiselTests/PrintableSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/PrintableSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 8e39d405..2ac2ad5d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -128,7 +128,7 @@ class PrintableSpec extends AnyFlatSpec with Matchers { printf(p"${FullName(myInst.io.fizz)}") } val firrtl = (new ChiselStage).emitChirrtl(new MyModule) - println(firrtl) // scalastyle:ignore regex + println(firrtl) getPrintfs(firrtl) match { case Seq(Printf("foo", Seq()), Printf("myWire.foo", Seq()), |