diff options
| author | Jack Koenig | 2018-11-21 15:34:42 -0800 |
|---|---|---|
| committer | Jack Koenig | 2018-12-04 13:13:13 -0800 |
| commit | 3db21bd8e5a32c29efa55494d180dac4d22589e5 (patch) | |
| tree | c21edf9bc9c5f2f42ec5716a829145024bb82862 /src/test/scala/chiselTests/MultiClockSpec.scala | |
| parent | 121635ed26c8a9852c827d6c0729515337604d08 (diff) | |
Add asBool, deprecate toBool
Diffstat (limited to 'src/test/scala/chiselTests/MultiClockSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MultiClockSpec.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala index 778806e3..88856009 100644 --- a/src/test/scala/chiselTests/MultiClockSpec.scala +++ b/src/test/scala/chiselTests/MultiClockSpec.scala @@ -55,7 +55,7 @@ class MultiClockSubModuleTest extends BasicTester { /** Test withReset changing the reset of a Reg */ class WithResetTest extends BasicTester { val reset2 = WireInit(false.B) - val reg = withReset(reset2 || reset.toBool) { RegInit(0.U(8.W)) } + val reg = withReset(reset2 || reset.asBool) { RegInit(0.U(8.W)) } reg := reg + 1.U val (cycle, done) = Counter(true.B, 10) |