diff options
| author | Jim Lawson | 2016-08-18 12:35:34 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-18 12:35:34 -0700 |
| commit | d18274e307271809db2c27676f1dca40a49c9627 (patch) | |
| tree | 2632a0e409bea3f9069c5ebfb555cc1ec04caa4f /src/test/scala/chiselTests/MulLookup.scala | |
| parent | ddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff) | |
| parent | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (diff) | |
Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests
Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
Diffstat (limited to 'src/test/scala/chiselTests/MulLookup.scala')
| -rw-r--r-- | src/test/scala/chiselTests/MulLookup.scala | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala index 831e323f..26ee4e03 100644 --- a/src/test/scala/chiselTests/MulLookup.scala +++ b/src/test/scala/chiselTests/MulLookup.scala @@ -8,11 +8,11 @@ import org.scalatest.prop._ import chisel3.testers.BasicTester class MulLookup(val w: Int) extends Module { - val io = new Bundle { - val x = UInt(INPUT, w) - val y = UInt(INPUT, w) - val z = UInt(OUTPUT, 2 * w) - } + val io = IO(new Bundle { + val x = Input(UInt.width(w)) + val y = Input(UInt.width(w)) + val z = Output(UInt.width(2 * w)) + }) val tbl = Vec( for { i <- 0 until 1 << w |