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authorAditya Naik2023-11-23 03:11:56 -0800
committerAditya Naik2023-11-23 03:11:56 -0800
commitaf415532cf160e63e971ceb301833b8433c18a50 (patch)
tree1fef70139846f57298c8e24a590490a74249f7dd /src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
parent8200c0cdf1d471453946d5ae24bc99757b2ef02d (diff)
cleanup
Diffstat (limited to 'src/test/scala/chiselTests/ModuleExplicitResetSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ModuleExplicitResetSpec.scala24
1 files changed, 0 insertions, 24 deletions
diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
deleted file mode 100644
index 1a55fb3f..00000000
--- a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests
-
-import chisel3.stage.ChiselStage
-
-class ModuleExplicitResetSpec extends ChiselFlatSpec {
-
- "A Module with an explicit reset in compatibility mode" should "elaborate" in {
- import Chisel._
- val myReset = true.B
- class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
- val io = new Bundle {
- val done = Bool(OUTPUT)
- }
-
- io.done := false.B
- }
-
- ChiselStage.elaborate {
- new ModuleExplicitReset(myReset)
- }
- }
-}