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authorJim Lawson2016-06-21 09:17:30 -0700
committerJim Lawson2016-06-21 09:17:30 -0700
commitd675043717593fb7e96fb0f1952debbeb7f20a57 (patch)
tree75efcd84a40d0520421d0d40d9b9cc9fdba6df8d /src/test/scala/chiselTests/Module.scala
parent53813f61b7dfe246d214ab966739d01c65c8ecb0 (diff)
New Module, IO, Input/Output wrapping.
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
-rw-r--r--src/test/scala/chiselTests/Module.scala22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 88ba795b..ba251916 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -4,20 +4,20 @@ package chiselTests
import Chisel._
class SimpleIO extends Bundle {
- val in = UInt(INPUT, 32)
- val out = UInt(OUTPUT, 32)
+ val in = Input(UInt(32))
+ val out = Output(UInt(32))
}
class PlusOne extends Module {
- val io = new SimpleIO
+ val io = IO(new SimpleIO)
io.out := io.in + UInt(1)
}
class ModuleVec(val n: Int) extends Module {
- val io = new Bundle {
- val ins = Vec(n, UInt(INPUT, 32))
- val outs = Vec(n, UInt(OUTPUT, 32))
- }
+ val io = IO(new Bundle {
+ val ins = Input(Vec(n, UInt(32)))
+ val outs = Output(Vec(n, UInt(32)))
+ })
val pluses = Vec.fill(n){ Module(new PlusOne).io }
for (i <- 0 until n) {
pluses(i).in := io.ins(i)
@@ -39,8 +39,8 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) {
*/
class ModuleWire extends Module {
- val io = new SimpleIO
- val inc = Wire(Module(new PlusOne).io)
+ val io = IO(new SimpleIO)
+ val inc = Wire(Module(new PlusOne).io.newType)
inc.in := io.in
io.out := inc.out
}
@@ -57,10 +57,10 @@ class ModuleWireTester(c: ModuleWire) extends Tester(c) {
*/
class ModuleWhen extends Module {
- val io = new Bundle {
+ val io = IO(new Bundle {
val s = new SimpleIO
val en = Bool()
- }
+ })
when(io.en) {
val inc = Module(new PlusOne).io
inc.in := io.s.in