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authorducky2016-11-17 13:01:03 -0800
committerducky2016-11-21 13:31:12 -0800
commit54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch)
tree7f6f9de04de6eb08878ac46be339fefc2a71395f /src/test/scala/chiselTests/Module.scala
parentcd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff)
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
-rw-r--r--src/test/scala/chiselTests/Module.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index c902d073..4f043f0a 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
import chisel3._
class SimpleIO extends Bundle {
- val in = Input(UInt.width(32))
- val out = Output(UInt.width(32))
+ val in = Input(UInt(32.W))
+ val out = Output(UInt(32.W))
}
class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
class ModuleVec(val n: Int) extends Module {
val io = IO(new Bundle {
- val ins = Input(Vec(n, UInt(32)))
- val outs = Output(Vec(n, UInt(32)))
+ val ins = Input(Vec(n, 32.U))
+ val outs = Output(Vec(n, 32.U))
})
val pluses = Vec.fill(n){ Module(new PlusOne).io }
for (i <- 0 until n) {