diff options
| author | Jim Lawson | 2016-07-19 15:08:22 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-19 15:08:22 -0700 |
| commit | 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 (patch) | |
| tree | e1a2aa9591ccc882a941d1ddbc9ded3218b5bc85 /src/test/scala/chiselTests/Module.scala | |
| parent | b27f29902d9f1d886e8edf1fc5e960cf9a634184 (diff) | |
Incorporate connection logic.
Compiles but fails tests.
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 7c0bc40e..f1608d5b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -41,7 +41,7 @@ class ModuleVecTester(c: ModuleVec) extends Tester(c) { class ModuleWire extends Module { val io = IO(new SimpleIO) - val inc = Wire(Module(new PlusOne).io.newType) + val inc = Wire(Module(new PlusOne).io.cloneType) inc.in := io.in io.out := inc.out } |