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authorJim Lawson2016-07-20 13:28:15 -0700
committerJim Lawson2016-07-20 13:28:15 -0700
commit28e80311f172ae4d1d477e8bb47ca3719c9a8fc5 (patch)
tree5d7a077498317c5f2412604380acc43c6b1fc371 /src/test/scala/chiselTests/Module.scala
parentf81202b896d30d90075be487895befa009b11733 (diff)
Compile ok.
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
Diffstat (limited to 'src/test/scala/chiselTests/Module.scala')
-rw-r--r--src/test/scala/chiselTests/Module.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index f1608d5b..857aeda3 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -11,7 +11,7 @@ class SimpleIO extends Bundle {
class PlusOne extends Module {
val io = IO(new SimpleIO)
- io.out := io.in + UInt(1)
+ io.out := io.in + 1.asUInt
}
class ModuleVec(val n: Int) extends Module {