diff options
| author | Schuyler Eldridge | 2019-05-09 20:13:54 -0400 |
|---|---|---|
| committer | GitHub | 2019-05-09 20:13:54 -0400 |
| commit | e02d25c2d9310291a3084821713bd8d9b2325651 (patch) | |
| tree | 82453617fec3957e33724eb3a0fd25dd060d803f /src/test/scala/chiselTests/LFSR16.scala | |
| parent | 6be76f79f873873497e40fa647f9456391b4d59a (diff) | |
| parent | 356d5c99c233540e4d993ccc365a7069d9d2beaa (diff) | |
Merge pull request #1092 from freechipsproject/lfsr-async-reset
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LFSR16.scala | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index 992bb4bf..d0f06865 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -51,10 +51,15 @@ class LFSRMaxPeriod(gen: => UInt) extends BasicTester { val seed = withReset(!started) { RegInit(rv) } val (_, wrap) = Counter(started, math.pow(2.0, rv.getWidth).toInt - 1) + when (rv === seed && started) { chisel3.assert(wrap) stop() } + + val last = RegNext(rv) + chisel3.assert(rv =/= last, "LFSR last value (0b%b) was equal to current value (0b%b)", rv, last) + } /** Check that the output of the new LFSR is the same asthe old LFSR */ |