diff options
| author | Jim Lawson | 2016-12-12 09:14:33 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-12 09:14:33 -0800 |
| commit | b581a24728bfba0c39ed2c032fd86f628a1e1a50 (patch) | |
| tree | f625219f936d39e760192aa69df17e776b95dd56 /src/test/scala/chiselTests/LFSR16.scala | |
| parent | 0bd9ae059368570dc72f25f7939afa5cfe5fd06e (diff) | |
| parent | ad53161bbb9f67e16b88ca7a508a537f88d77e05 (diff) | |
Merge branch 'master' into buildinfousepackageaspath
Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LFSR16.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index b13b67e3..09beddb9 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -9,9 +9,9 @@ import chisel3.util._ class LFSR16 extends Module { val io = IO(new Bundle { val inc = Input(Bool()) - val out = Output(UInt.width(16)) + val out = Output(UInt(16.W)) }) - val res = Reg(init = UInt(1, 16)) + val res = Reg(init = 1.U(16.W)) when (io.inc) { val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) res := nxt_res |