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authorJim Lawson2016-10-06 08:57:10 -0700
committerJim Lawson2016-10-06 08:57:10 -0700
commit82625071405672eb4a19363d6f73f359ac28a7f5 (patch)
treedee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/test/scala/chiselTests/LFSR16.scala
parentb7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff)
parent7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff)
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
-rw-r--r--src/test/scala/chiselTests/LFSR16.scala16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index ed76a296..b13b67e3 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -1,14 +1,16 @@
// See LICENSE for license details.
package chiselTests
-import Chisel._
-import Chisel.testers.BasicTester
+
+import chisel3._
+import chisel3.testers.BasicTester
+import chisel3.util._
class LFSR16 extends Module {
- val io = new Bundle {
- val inc = Bool(INPUT)
- val out = UInt(OUTPUT, 16)
- }
+ val io = IO(new Bundle {
+ val inc = Input(Bool())
+ val out = Output(UInt.width(16))
+ })
val res = Reg(init = UInt(1, 16))
when (io.inc) {
val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
@@ -34,7 +36,7 @@ class LFSR16Tester(c: LFSR16) extends Tester(c) {
}
*/
-//TODO: Use chisel.util version instead?
+//TODO: Use chisel3.util version instead?
class LFSRSpec extends ChiselPropSpec {