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authorAlbert Magyar2020-07-21 17:40:16 -0700
committerGitHub2020-07-21 17:40:16 -0700
commit473a13877c60ba9fb13de47542a8397412c2b967 (patch)
tree159cec6aa6ece2e87ceffbdc56a553fe71d0726b /src/test/scala/chiselTests/IntervalSpec.scala
parent4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff)
parente5568f55a6a149adfd19ad04b264a69078288f86 (diff)
Merge pull request #1519 from freechipsproject/no-scalastyle
Remove scalastyle configurations
Diffstat (limited to 'src/test/scala/chiselTests/IntervalSpec.scala')
-rw-r--r--src/test/scala/chiselTests/IntervalSpec.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala
index 1f813442..0babed41 100644
--- a/src/test/scala/chiselTests/IntervalSpec.scala
+++ b/src/test/scala/chiselTests/IntervalSpec.scala
@@ -19,7 +19,6 @@ import firrtl.{FIRRTLException, HighFirrtlCompiler, LowFirrtlCompiler, MiddleFir
import org.scalatest.freespec.AnyFreeSpec
import org.scalatest.matchers.should.Matchers
-//scalastyle:off magic.number
//noinspection TypeAnnotation
object IntervalTestHelper {
@@ -30,7 +29,6 @@ object IntervalTestHelper {
* @param gen the generator for the module
* @return the Verilog code as a string.
*/
- //scalastyle:off cyclomatic.complexity
def makeFirrtl[T <: RawModule](compilerName: String)(gen: () => T): String = {
(new ChiselStage)
.execute(Array("--compiler", compilerName,