summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/IllegalRefSpec.scala
diff options
context:
space:
mode:
authorJack2022-01-12 04:27:19 +0000
committerJack2022-01-12 04:27:19 +0000
commit29df513e348cc809876893f650af8180f0190496 (patch)
tree06daaea954b4e5af7113f06e4bdbb78b33515cb3 /src/test/scala/chiselTests/IllegalRefSpec.scala
parent5242ce90659decb9058ee75db56e5c188029fbf9 (diff)
parent747d16311bdf185d2e98e452b14cb5d8ccca004c (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'src/test/scala/chiselTests/IllegalRefSpec.scala')
-rw-r--r--src/test/scala/chiselTests/IllegalRefSpec.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/IllegalRefSpec.scala b/src/test/scala/chiselTests/IllegalRefSpec.scala
index 1bafc780..219df5af 100644
--- a/src/test/scala/chiselTests/IllegalRefSpec.scala
+++ b/src/test/scala/chiselTests/IllegalRefSpec.scala
@@ -39,7 +39,7 @@ object IllegalRefSpec {
val o = Output(Bool())
})
private var tmp: Option[Bool] = None
- when (io.i) {
+ when(io.i) {
val x = io.i & io.i
tmp = Some(x)
}
@@ -60,13 +60,13 @@ class IllegalRefSpec extends ChiselFlatSpec with Utils {
variants.foreach {
case (k, v) =>
s"Illegal cross-module references in ${k}" should "fail" in {
- a [ChiselException] should be thrownBy extractCause[ChiselException] {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
ChiselStage.elaborate { new IllegalRefOuter(v) }
}
}
s"Using a signal that has escaped its enclosing when scope in ${k}" should "fail" in {
- a [ChiselException] should be thrownBy extractCause[ChiselException] {
+ a[ChiselException] should be thrownBy extractCause[ChiselException] {
ChiselStage.elaborate { new CrossWhenConnect(v) }
}
}