Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests

Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk

1 files changed, 45 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
new file mode 100644
index 00000000..edbd3d09
--- /dev/null
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import Chisel._
+
+class IOCSimpleIO extends Bundle {
+  val in  = UInt(INPUT,  32)
+  val out = UInt(OUTPUT, 32)
+}
+
+class IOCPlusOne extends Module {
+  val io = new IOCSimpleIO
+  io.out := io.in + UInt(1)
+}
+
+class IOCModuleVec(val n: Int) extends Module {
+  val io = new Bundle {
+    val ins  = Vec(n, UInt(INPUT,  32))
+    val outs = Vec(n, UInt(OUTPUT, 32))
+  }
+  val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
+  for (i <- 0 until n) {
+    pluses(i).in := io.ins(i)
+    io.outs(i)   := pluses(i).out
+  }
+}
+
+class IOCModuleWire extends Module {
+  val io = new IOCSimpleIO
+  val inc = Wire(Module(new IOCPlusOne).io.chiselCloneType)
+  inc.in := io.in
+  io.out := inc.out
+}
+
+class IOCompatibilitySpec extends ChiselPropSpec {
+
+  property("IOCModuleVec should elaborate") {
+    elaborate { new IOCModuleVec(2) }
+  }
+
+  property("IOCModuleWire should elaborate") {
+    elaborate { new IOCModuleWire }
+  }
+}