summaryrefslogtreecommitdiff
path: root/src/test/scala/chiselTests/ExtModule.scala
diff options
context:
space:
mode:
authorSchuyler Eldridge2020-06-22 20:34:46 -0400
committerGitHub2020-06-22 20:34:46 -0400
commit9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch)
treeac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/ExtModule.scala
parentd099d01ae6b11d8befdf7b32ab74c3167a552984 (diff)
parentb5e59895e13550006fd8e951b7e9483de00f82dd (diff)
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/ExtModule.scala')
-rw-r--r--src/test/scala/chiselTests/ExtModule.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala
index 0349d180..582a05ae 100644
--- a/src/test/scala/chiselTests/ExtModule.scala
+++ b/src/test/scala/chiselTests/ExtModule.scala
@@ -4,6 +4,7 @@ package chiselTests
import chisel3._
import chisel3.experimental._
+import chisel3.stage.ChiselStage
import chisel3.testers.BasicTester
// Avoid collisions with regular BlackBox tests by putting ExtModule blackboxes
@@ -68,7 +69,7 @@ class ExtModuleSpec extends ChiselFlatSpec {
Seq("/chisel3/BlackBoxTest.v"))
}
"DataMirror.modulePorts" should "work with ExtModule" in {
- elaborate(new Module {
+ ChiselStage.elaborate(new Module {
val io = IO(new Bundle { })
val m = Module(new ExtModule.BlackBoxPassthrough)
assert(DataMirror.modulePorts(m) == Seq(