Merge pull request #1519 from freechipsproject/no-scalastyle

Remove scalastyle configurations

1 files changed, 1 insertions, 3 deletions

diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f023df8..fd3249fd 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -23,14 +23,13 @@ class EnableShiftRegister extends Module {
   io.out := r3
 }
 
-// scalastyle:off regex
 /*
 class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   val reg = Array.fill(4){ 0 }
   for (t <- 0 until 16) {
     val in    = rnd.nextInt(16)
     val shift = rnd.nextInt(2)
-    println("SHIFT " + shift + " IN " + in)   // scalastyle:ignore regex
+    println("SHIFT " + shift + " IN " + in)
     poke(c.io.in,    in)
     poke(c.io.shift, shift)
     step(1)
@@ -43,7 +42,6 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) {
   }
 }
 */
-// scalastyle:on regex
 
 class EnableShiftRegisterSpec extends ChiselPropSpec {