Don't invalidate ExtModule ports in an explicitInvalidate = true context (backport #2795) (#2799)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795)

* Don't invalidate ExtModule ports in an explicitInvalidate = true context

ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`.

(cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d)

# Conflicts:
#	core/src/main/scala/chisel3/BlackBox.scala

* Resolve backport conflicts

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

1 files changed, 22 insertions, 0 deletions

diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index 41cfbec4..5a3b43e6 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -614,4 +614,26 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     ChiselStage.elaborate(new MyModule)
   }
 
+  behavior.of("BlackBox")
+
+  it should "have invalidated ports in a compatibility context" in {
+    class ExtModuleInvalidatedTester extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(8.W))
+        val out = Output(UInt(8.W))
+      })
+      val inst = Module(new BlackBox {
+        val io = IO(new Bundle {
+          val in = Input(UInt(8.W))
+          val out = Output(UInt(8.W))
+        })
+      })
+      inst.io.in := io.in
+      io.out := inst.io.out
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new ExtModuleInvalidatedTester)
+    chirrtl should include("inst.in is invalid")
+    chirrtl should include("inst.out is invalid")
+  }
 }