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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
index 40358d11..451ba885 100644
--- a/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
+++ b/src/test/scala/chiselTests/ChiselTestUtilitiesSpec.scala
@@ -38,7 +38,7 @@ class ChiselTestUtilitiesSpec extends ChiselFlatSpec {
}
it should "error if the expected width is wrong" in {
- a [TestFailedException] shouldBe thrownBy {
+ a[TestFailedException] shouldBe thrownBy {
assertInferredWidth(8) {
val w = Wire(UInt())
w := 2.U(2.W)