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authorChick Markley2021-04-27 12:17:17 -0700
committerGitHub2021-04-27 12:17:17 -0700
commit6deb379b1d8bafc81a605f60476bf0f24eac60b4 (patch)
treeb12c7dfaea1948ec9a7fa2f389db0699b3d1daf4 /src/test/scala/chiselTests/ChiselSpec.scala
parent23b3fe8a6a2db92599bb0775626425056d47d1de (diff)
Introduce VecLiterals (#1834)
This PR provides for support for Vec literals. They can be one of two forms Inferred: ``` Vec.Lit(0x1.U, 0x2.U) ``` or explicit: ``` Vec(2, UInt(4.W)).Lit(0 -> 0x1.U, 1 -> 0x2.U) ``` - Explicit form allows for partial, or sparse, literals. - Vec literals can be used as Register initializers - Arbitrary nesting (consistent with type constraints is allowed)
Diffstat (limited to 'src/test/scala/chiselTests/ChiselSpec.scala')
-rw-r--r--src/test/scala/chiselTests/ChiselSpec.scala25
1 files changed, 14 insertions, 11 deletions
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 8df680d6..9503089a 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -2,22 +2,22 @@
package chiselTests
-import org.scalatest._
-import org.scalatest.prop._
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalacheck._
import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import chisel3.aop.Aspect
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage, NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation}
import chisel3.testers._
-import firrtl.{AnnotationSeq, CommonOptions, EmittedVerilogCircuitAnnotation, ExecutionOptionsManager, FirrtlExecutionFailure, FirrtlExecutionSuccess, HasFirrtlOptions}
-import firrtl.annotations.{Annotation, DeletedAnnotation}
+import firrtl.annotations.Annotation
import firrtl.util.BackendCompilationUtilities
+import firrtl.{AnnotationSeq, EmittedVerilogCircuitAnnotation}
+import org.scalacheck._
+import org.scalatest._
+import org.scalatest.flatspec.AnyFlatSpec
+import org.scalatest.freespec.AnyFreeSpec
+import org.scalatest.matchers.should._
+import org.scalatestplus.scalacheck.ScalaCheckPropertyChecks
+
import java.io.ByteArrayOutputStream
import java.security.Permission
-
-import chisel3.aop.Aspect
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage, NoRunFirrtlCompilerAnnotation, PrintFullStackTraceAnnotation}
-import org.scalatestplus.scalacheck.ScalaCheckPropertyChecks
import scala.reflect.ClassTag
/** Common utility functions for Chisel unit tests. */
@@ -90,6 +90,9 @@ trait ChiselRunners extends Assertions with BackendCompilationUtilities {
/** Spec base class for BDD-style testers. */
abstract class ChiselFlatSpec extends AnyFlatSpec with ChiselRunners with Matchers
+/** Spec base class for BDD-style testers. */
+abstract class ChiselFreeSpec extends AnyFreeSpec with ChiselRunners with Matchers
+
/** Spec base class for property-based testers. */
abstract class ChiselPropSpec extends PropSpec with ChiselRunners with ScalaCheckPropertyChecks with Matchers {