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authorducky2015-12-11 14:25:42 -0800
committerducky2015-12-11 17:16:30 -0800
commitdbd072172f6312893e1922e48ed768ae0fab9a89 (patch)
treec3a0f10dd286ae2bba50c31b987ab39c45189898 /src/test/scala/chiselTests/BundleWire.scala
parentbffc67c2bbeb107d2ff9903aa35e85fbb7da73f9 (diff)
Refactor tests to use stop() and assert() instead of io.error/io.done
Gate assert, printf, stop by reset Fix testbenches that never worked Change simulation prints to display cycle at which test was signaled to end, not when simulator stops Better documentation for Counter
Diffstat (limited to 'src/test/scala/chiselTests/BundleWire.scala')
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 5beed039..128b2c5f 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -25,10 +25,13 @@ class BundleWire(n: Int) extends Module {
class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
val dut = Module(new BundleWire(n))
- io.done := Bool(true)
dut.io.in.x := UInt(x)
dut.io.in.y := UInt(y)
- io.error := dut.io.outs.map(o => o.x != UInt(x) || o.y != UInt(y)).foldLeft(UInt(0))(_##_)
+ for (elt <- dut.io.outs) {
+ assert(elt.x === UInt(x))
+ assert(elt.y === UInt(y))
+ }
+ stop()
}
class BundleWireSpec extends ChiselPropSpec {