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authorAndrew Waterman2016-02-04 00:00:19 -0800
committerAndrew Waterman2016-02-04 00:00:19 -0800
commit62fa95acc5d3d301fe461c5844c29d0c75ca6a5d (patch)
tree89893f19fba9aacc7e18ba8013b428e9f1e03482 /src/test/scala/chiselTests/BundleWire.scala
parent7fc2ea6a14da441db9c47d094361fea07436f6d3 (diff)
parentc5240a3bfe1c05a206c7c34c3c7c5007bbcc3680 (diff)
Merge branch 'blackbox't push origin master
Diffstat (limited to 'src/test/scala/chiselTests/BundleWire.scala')
-rw-r--r--src/test/scala/chiselTests/BundleWire.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 128b2c5f..bef56a56 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -38,7 +38,7 @@ class BundleWireSpec extends ChiselPropSpec {
property("All vec elems should match the inputs") {
forAll(vecSizes, safeUInts, safeUInts) { (n: Int, x: Int, y: Int) =>
- assert(execute{ new BundleWireTester(n, x, y) })
+ assertTesterPasses{ new BundleWireTester(n, x, y) }
}
}
}