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authorJack Koenig2021-01-21 22:50:12 -0800
committerGitHub2021-01-21 22:50:12 -0800
commitdd6871b8b3f2619178c2a333d9d6083805d99e16 (patch)
tree825776855e7d2fc28ef32ebb05df7339c24e00b3 /src/test/scala/chiselTests/BoringUtilsSpec.scala
parent616256c35cb7de8fcd97df56af1986b747abe54d (diff)
parent53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (diff)
Merge pull request #1745 from chipsalliance/remove-val-io
Remove "val io" and rename MultiIOModule to Module
Diffstat (limited to 'src/test/scala/chiselTests/BoringUtilsSpec.scala')
-rw-r--r--src/test/scala/chiselTests/BoringUtilsSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 0500ac23..39859581 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -71,7 +71,7 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners {
out := x
}
- class Top(val width: Int) extends MultiIOModule {
+ class Top(val width: Int) extends Module {
/* From the perspective of deduplication, all sources are identical and all sinks are identical. */
val sources = Seq.fill(3)(Module(new Source))
val sinks = Seq.fill(6)(Module(new Sink))