Merge pull request #265 from ucb-bar/gsdt

Gsdt - Fixup to Chisel connections and direction - PR 200 revisited.

1 files changed, 17 insertions, 16 deletions

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index fdc5970e..344754e1 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -8,27 +8,28 @@ import org.scalatest._
 import chisel3._
 import chisel3.testers.BasicTester
 import chisel3.util._
+//import chisel3.core.ExplicitCompileOptions.Strict
 
 class BlackBoxInverter extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxPassthrough extends BlackBox {
-  val io = new Bundle() {
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxRegister extends BlackBox {
-  val io = new Bundle() {
-    val clock = Clock().asInput
-    val in = Bool(INPUT)
-    val out = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle() {
+    val clock = Input(Clock())
+    val in = Input(Bool())
+    val out = Output(Bool())
+  })
 }
 
 class BlackBoxTester extends BasicTester {
@@ -86,9 +87,9 @@ class BlackBoxWithClockTester extends BasicTester {
 /*
 // Must determine how to handle parameterized Verilog
 class BlackBoxConstant(value: Int) extends BlackBox {
-  val io = new Bundle() {
-    val out = UInt(width=log2Up(value)).asOutput
-  }
+  val io = IO(new Bundle() {
+    val out = Output(UInt(width=log2Up(value)))
+  })
   override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
 }