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| author | Jiuyang Liu | 2021-02-04 00:36:12 +0000 |
|---|---|---|
| committer | GitHub | 2021-02-03 16:36:12 -0800 |
| commit | f45216effc573d33d4aa4e525cff955ab332efbd (patch) | |
| tree | ea4f52f98e4bf3746ee0b8b6df10f37c13941825 /src/test/scala/chiselTests/AsyncResetSpec.scala | |
| parent | 98ce9194e5d87fdd5be931b6cd516d180a6540cd (diff) | |
Remove Deprecated APIs (#1730)
Diffstat (limited to 'src/test/scala/chiselTests/AsyncResetSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AsyncResetSpec.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/AsyncResetSpec.scala b/src/test/scala/chiselTests/AsyncResetSpec.scala index a8e62fe8..d49f390c 100644 --- a/src/test/scala/chiselTests/AsyncResetSpec.scala +++ b/src/test/scala/chiselTests/AsyncResetSpec.scala @@ -209,7 +209,6 @@ class AsyncResetSpec extends ChiselFlatSpec with Utils { } it should "support Fixed regs" in { - import chisel3.experimental.{withReset => _, _} assertTesterPasses(new BasicTester { val reg = withReset(reset.asAsyncReset)(RegNext(-6.0.F(2.BP), 3.F(2.BP))) val (count, done) = Counter(true.B, 4) @@ -223,7 +222,7 @@ class AsyncResetSpec extends ChiselFlatSpec with Utils { } it should "support Interval regs" in { - import chisel3.experimental.{withReset => _, _} + import chisel3.experimental._ assertTesterPasses(new BasicTester { val reg = withReset(reset.asAsyncReset) { val x = RegInit(Interval(range"[0,13]"), 13.I) |