diff options
| author | Schuyler Eldridge | 2020-06-22 20:34:46 -0400 |
|---|---|---|
| committer | GitHub | 2020-06-22 20:34:46 -0400 |
| commit | 9f44b593efe4830aeb56d17f5ed59277a74832f8 (patch) | |
| tree | ac43010dd7fc2a14303497f95e12f2a40bb16d0e /src/test/scala/chiselTests/AsyncResetSpec.scala | |
| parent | d099d01ae6b11d8befdf7b32ab74c3167a552984 (diff) | |
| parent | b5e59895e13550006fd8e951b7e9483de00f82dd (diff) | |
Merge pull request #1481 from freechipsproject/driver-deprecations
Remove Deprecated Usages of chisel3.Driver, CircuitForm
Diffstat (limited to 'src/test/scala/chiselTests/AsyncResetSpec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/AsyncResetSpec.scala | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/test/scala/chiselTests/AsyncResetSpec.scala b/src/test/scala/chiselTests/AsyncResetSpec.scala index a6bf3a8a..4f1bd134 100644 --- a/src/test/scala/chiselTests/AsyncResetSpec.scala +++ b/src/test/scala/chiselTests/AsyncResetSpec.scala @@ -3,6 +3,7 @@ package chiselTests import chisel3._ +import chisel3.stage.ChiselStage import chisel3.util.{Counter, Queue} import chisel3.testers.BasicTester import firrtl.checks.CheckResets.NonLiteralAsyncResetValueException @@ -137,22 +138,22 @@ class AsyncResetDontCareModule extends RawModule { bulkAggPort <> DontCare } -class AsyncResetSpec extends ChiselFlatSpec { +class AsyncResetSpec extends ChiselFlatSpec with Utils { behavior of "AsyncReset" it should "be able to be connected to DontCare" in { - elaborate(new AsyncResetDontCareModule) + ChiselStage.elaborate(new AsyncResetDontCareModule) } it should "be allowed with literal reset values" in { - elaborate(new BasicTester { + ChiselStage.elaborate(new BasicTester { withReset(reset.asAsyncReset)(RegInit(123.U)) }) } it should "NOT be allowed with non-literal reset values" in { - a [NonLiteralAsyncResetValueException] shouldBe thrownBy { + a [NonLiteralAsyncResetValueException] should be thrownBy extractCause[NonLiteralAsyncResetValueException] { compile(new BasicTester { val x = WireInit(123.U + 456.U) withReset(reset.asAsyncReset)(RegInit(x)) @@ -161,8 +162,8 @@ class AsyncResetSpec extends ChiselFlatSpec { } it should "NOT be allowed to connect directly to a Bool" in { - a [ChiselException] shouldBe thrownBy { - elaborate(new BasicTester { + a [ChiselException] should be thrownBy extractCause[ChiselException] { + ChiselStage.elaborate(new BasicTester { val bool = Wire(Bool()) val areset = reset.asAsyncReset bool := areset @@ -179,7 +180,7 @@ class AsyncResetSpec extends ChiselFlatSpec { } it should "allow casting to and from Bool" in { - elaborate(new BasicTester { + ChiselStage.elaborate(new BasicTester { val r: Reset = reset val a: AsyncReset = WireInit(r.asAsyncReset) val b: Bool = a.asBool |
