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authorJim Lawson2017-05-11 15:07:30 -0700
committerGitHub2017-05-11 15:07:30 -0700
commit8baa2ab806be1aa85a7a1da7b348726da1bd1d19 (patch)
tree9c6251d52cb17830a9ce212c7630bf0d9fecf002 /src/test/scala/chiselTests/AnalogIntegrationSpec.scala
parent45e235a5948a1cd15b8ccb5f437dc6f2ff80cb96 (diff)
Scope resources - move them down into chisel3 directory - fixes #549 (#610)
Diffstat (limited to 'src/test/scala/chiselTests/AnalogIntegrationSpec.scala')
-rw-r--r--src/test/scala/chiselTests/AnalogIntegrationSpec.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
index de717c4f..952d3872 100644
--- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
+++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala
@@ -126,10 +126,10 @@ class AnalogIntegrationTester(mod: => AnalogDUTModule) extends BasicTester {
class AnalogIntegrationSpec extends ChiselFlatSpec {
behavior of "Verilator"
it should "support simple bidirectional wires" in {
- assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/AnalogBlackBox.v"))
+ assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/chisel3/AnalogBlackBox.v"))
}
// Use this test once Verilator supports alias
ignore should "support arbitrary bidirectional wires" in {
- assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/AnalogBlackBox.v"))
+ assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/chisel3/AnalogBlackBox.v"))
}
}