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authorAditya Naik2023-11-23 03:11:56 -0800
committerAditya Naik2023-11-23 03:11:56 -0800
commitaf415532cf160e63e971ceb301833b8433c18a50 (patch)
tree1fef70139846f57298c8e24a590490a74249f7dd /src/test/scala/chiselTests/AdderTree.scala
parent8200c0cdf1d471453946d5ae24bc99757b2ef02d (diff)
cleanup
Diffstat (limited to 'src/test/scala/chiselTests/AdderTree.scala')
-rw-r--r--src/test/scala/chiselTests/AdderTree.scala35
1 files changed, 0 insertions, 35 deletions
diff --git a/src/test/scala/chiselTests/AdderTree.scala b/src/test/scala/chiselTests/AdderTree.scala
deleted file mode 100644
index 29ef97a4..00000000
--- a/src/test/scala/chiselTests/AdderTree.scala
+++ /dev/null
@@ -1,35 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chiselTests
-
-import chisel3._
-import chisel3.testers.BasicTester
-
-class AdderTree[T <: Bits with Num[T]](genType: T, vecSize: Int) extends Module {
- val io = IO(new Bundle {
- val numIn = Input(Vec(vecSize, genType))
- val numOut = Output(genType)
- })
- io.numOut := io.numIn.reduceTree((a: T, b: T) => (a + b))
-}
-
-class AdderTreeTester(bitWidth: Int, numsToAdd: List[Int]) extends BasicTester {
- val genType = UInt(bitWidth.W)
- val dut = Module(new AdderTree(genType, numsToAdd.size))
- dut.io.numIn := VecInit(numsToAdd.map(x => x.asUInt(bitWidth.W)))
- val sumCorrect = dut.io.numOut === (numsToAdd.reduce(_ + _) % (1 << bitWidth)).asUInt(bitWidth.W)
- assert(sumCorrect)
- stop()
-}
-
-class AdderTreeSpec extends ChiselPropSpec {
- property("All numbers should be added correctly by an Adder Tree") {
- forAll(safeUIntN(20)) {
- case (w: Int, v: List[Int]) => {
- whenever(v.size > 0 && w > 0) {
- assertTesterPasses { new AdderTreeTester(w, v.map(x => math.abs(x) % (1 << w)).toList) }
- }
- }
- }
- }
-}