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| author | Jim Lawson | 2015-07-24 17:17:01 -0700 |
|---|---|---|
| committer | Jim Lawson | 2015-07-24 17:17:01 -0700 |
| commit | e73450165c59d68b524689a7169e03140a41a1c5 (patch) | |
| tree | b7236f80d9abf60775ecbcefe6f7ca25557dce73 /src/test/scala/ChiselTests/VecShiftRegister.scala | |
| parent | 94893bad972ded686a2c68dd334aa40b92e3b85d (diff) | |
| parent | 3976145bb8c7595ad0f0a7fbb4ccbbd3030d8873 (diff) | |
Merge pull request #1 from ucb-bar/packagedir
Packagedir
Diffstat (limited to 'src/test/scala/ChiselTests/VecShiftRegister.scala')
| -rw-r--r-- | src/test/scala/ChiselTests/VecShiftRegister.scala | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/test/scala/ChiselTests/VecShiftRegister.scala b/src/test/scala/ChiselTests/VecShiftRegister.scala new file mode 100644 index 00000000..7a761801 --- /dev/null +++ b/src/test/scala/ChiselTests/VecShiftRegister.scala @@ -0,0 +1,28 @@ +package ChiselTests +import Chisel._ + +class VecShiftRegister extends Module { + val io = new Bundle { + val ins = Vec(UInt(INPUT, 4), 4) + val load = Bool(INPUT) + val shift = Bool(INPUT) + val out = UInt(OUTPUT, 4) + } + val delays = Reg(Vec(UInt(width = 4), 4)) + when (io.load) { + delays(0) := io.ins(0) + delays(1) := io.ins(1) + delays(2) := io.ins(2) + delays(3) := io.ins(3) + } .elsewhen(io.shift) { + delays(0) := io.ins(0) + delays(1) := delays(0) + delays(2) := delays(1) + delays(3) := delays(2) + } + io.out := delays(3) +} + + +class VecShiftRegisterTester(c: VecShiftRegister) extends Tester(c) { +} |
