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authorJim Lawson2015-07-24 17:17:01 -0700
committerJim Lawson2015-07-24 17:17:01 -0700
commite73450165c59d68b524689a7169e03140a41a1c5 (patch)
treeb7236f80d9abf60775ecbcefe6f7ca25557dce73 /src/test/scala/ChiselTests/LFSR16.scala
parent94893bad972ded686a2c68dd334aa40b92e3b85d (diff)
parent3976145bb8c7595ad0f0a7fbb4ccbbd3030d8873 (diff)
Merge pull request #1 from ucb-bar/packagedir
Packagedir
Diffstat (limited to 'src/test/scala/ChiselTests/LFSR16.scala')
-rw-r--r--src/test/scala/ChiselTests/LFSR16.scala30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/test/scala/ChiselTests/LFSR16.scala b/src/test/scala/ChiselTests/LFSR16.scala
new file mode 100644
index 00000000..2683247f
--- /dev/null
+++ b/src/test/scala/ChiselTests/LFSR16.scala
@@ -0,0 +1,30 @@
+package ChiselTests
+import Chisel._
+
+class LFSR16 extends Module {
+ val io = new Bundle {
+ val inc = Bool(INPUT)
+ val out = UInt(OUTPUT, 16)
+ }
+ val res = Reg(init = UInt(1, 16))
+ when (io.inc) {
+ val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
+ res := nxt_res
+ }
+ io.out := res
+}
+
+
+class LFSR16Tester(c: LFSR16) extends Tester(c) {
+ var res = 1
+ for (t <- 0 until 16) {
+ val inc = rnd.nextInt(2)
+ poke(c.io.inc, inc)
+ step(1)
+ if (inc == 1) {
+ val bit = ((res >> 0) ^ (res >> 2) ^ (res >> 3) ^ (res >> 5) ) & 1;
+ res = (res >> 1) | (bit << 15);
+ }
+ expect(c.io.out, res)
+ }
+}