summaryrefslogtreecommitdiff
path: root/src/main/scala/chisel3/util/random/PRNG.scala
diff options
context:
space:
mode:
authorJiuyang Liu2021-11-14 12:43:01 +0800
committerGitHub2021-11-14 12:43:01 +0800
commit6c5ea6781b0850888e7d0d44439df07146665534 (patch)
treed7a7a028cecbbe3bbcb1c91984b7db250cc4b606 /src/main/scala/chisel3/util/random/PRNG.scala
parent74ebcbca5a7394b67cd8c0d9fd35e32426759500 (diff)
parent64ad1c06b588ba75839e2629fbf889d7b8604953 (diff)
Merge branch 'master' into update/sbt-unidoc-0.5.0
Diffstat (limited to 'src/main/scala/chisel3/util/random/PRNG.scala')
-rw-r--r--src/main/scala/chisel3/util/random/PRNG.scala13
1 files changed, 10 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala
index 9b42acf1..3a44385a 100644
--- a/src/main/scala/chisel3/util/random/PRNG.scala
+++ b/src/main/scala/chisel3/util/random/PRNG.scala
@@ -7,16 +7,23 @@ import chisel3.util.Valid
/** Pseudo Random Number Generators (PRNG) interface
* @param n the width of the LFSR
+ * @groupdesc Signals The actual hardware fields of the Bundle
*/
class PRNGIO(val n: Int) extends Bundle {
- /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state) */
+ /** A [[chisel3.util.Valid Valid]] interface that can be used to set the seed (internal PRNG state)
+ * @group Signals
+ */
val seed: Valid[Vec[Bool]] = Input(Valid(Vec(n, Bool())))
- /** When asserted, the PRNG will increment by one */
+ /** When asserted, the PRNG will increment by one
+ * @group Signals
+ */
val increment: Bool = Input(Bool())
- /** The current state of the PRNG */
+ /** The current state of the PRNG
+ * @group Signals
+ */
val out: Vec[Bool] = Output(Vec(n, Bool()))
}