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authorSchuyler Eldridge2019-05-09 20:13:54 -0400
committerGitHub2019-05-09 20:13:54 -0400
commite02d25c2d9310291a3084821713bd8d9b2325651 (patch)
tree82453617fec3957e33724eb3a0fd25dd060d803f /src/main/scala/chisel3/util/random/GaloisLFSR.scala
parent6be76f79f873873497e40fa647f9456391b4d59a (diff)
parent356d5c99c233540e4d993ccc365a7069d9d2beaa (diff)
Merge pull request #1092 from freechipsproject/lfsr-async-reset
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
Diffstat (limited to 'src/main/scala/chisel3/util/random/GaloisLFSR.scala')
-rw-r--r--src/main/scala/chisel3/util/random/GaloisLFSR.scala16
1 files changed, 6 insertions, 10 deletions
diff --git a/src/main/scala/chisel3/util/random/GaloisLFSR.scala b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
index 3a61df95..85a6afde 100644
--- a/src/main/scala/chisel3/util/random/GaloisLFSR.scala
+++ b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
@@ -45,18 +45,14 @@ class GaloisLFSR(
step: Int = 1,
updateSeed: Boolean = false) extends PRNG(width, seed, step, updateSeed) with LFSR {
- def delta(s: UInt): UInt = {
- val in = s.asBools
- val first = in.head
- val out = Wire(Vec(s.getWidth, Bool()))
- out
- .zip(in.tail :+ first)
+ def delta(s: Seq[Bool]): Seq[Bool] = {
+ val first = s.head
+ (s.tail :+ first)
.zipWithIndex
- .foreach {
- case ((l, r), i) if taps(i + 1) && (i + 1 != out.size) => l := reduction(r, first)
- case ((l, r), _) => l := r
+ .map {
+ case (a, i) if taps(i + 1) && (i + 1 != s.size) => reduction(a, first)
+ case (a, _) => a
}
- out.asUInt
}
}