diff options
| author | Schuyler Eldridge | 2019-05-09 20:13:54 -0400 |
|---|---|---|
| committer | GitHub | 2019-05-09 20:13:54 -0400 |
| commit | e02d25c2d9310291a3084821713bd8d9b2325651 (patch) | |
| tree | 82453617fec3957e33724eb3a0fd25dd060d803f /src/main/scala/chisel3/util/random/FibonacciLFSR.scala | |
| parent | 6be76f79f873873497e40fa647f9456391b4d59a (diff) | |
| parent | 356d5c99c233540e4d993ccc365a7069d9d2beaa (diff) | |
Merge pull request #1092 from freechipsproject/lfsr-async-reset
LFSR/PRNG Asynchronous Safety, Use Vec[Bool] to store internal state
Diffstat (limited to 'src/main/scala/chisel3/util/random/FibonacciLFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/random/FibonacciLFSR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/random/FibonacciLFSR.scala b/src/main/scala/chisel3/util/random/FibonacciLFSR.scala index 53a42320..c61f0210 100644 --- a/src/main/scala/chisel3/util/random/FibonacciLFSR.scala +++ b/src/main/scala/chisel3/util/random/FibonacciLFSR.scala @@ -47,7 +47,7 @@ class FibonacciLFSR( step: Int = 1, updateSeed: Boolean = false) extends PRNG(width, seed, step, updateSeed) with LFSR { - def delta(s: UInt): UInt = s(width-2,0) ## taps.map{ case i => s(i - 1) }.reduce(reduction) + def delta(s: Seq[Bool]): Seq[Bool] = taps.map{ case i => s(i - 1) }.reduce(reduction) +: s.dropRight(1) } |