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authorJack Koenig2022-01-10 16:32:51 -0800
committerGitHub2022-01-10 16:32:51 -0800
commit2b48fd15a7711dcd44334fbbc538667a102a581a (patch)
tree4b4766347c3943d65c13e5de2d139b14821eec61 /src/main/scala/chisel3/util/pla.scala
parent92e77a97af986629766ac9038f0ebc8ab9a48fa1 (diff)
parentbff8dc0738adafa1176f6959a33ad86f6373c558 (diff)
Merge pull request #2246 from chipsalliance/scalafmt
Add scalafmt configuration and apply it.
Diffstat (limited to 'src/main/scala/chisel3/util/pla.scala')
-rw-r--r--src/main/scala/chisel3/util/pla.scala35
1 files changed, 18 insertions, 17 deletions
diff --git a/src/main/scala/chisel3/util/pla.scala b/src/main/scala/chisel3/util/pla.scala
index c57ca962..d4707d26 100644
--- a/src/main/scala/chisel3/util/pla.scala
+++ b/src/main/scala/chisel3/util/pla.scala
@@ -68,7 +68,8 @@ object pla {
val inverterMask = invert.value & invert.mask
if (inverterMask.bitCount != 0)
- require(invert.getWidth == numberOfOutputs,
+ require(
+ invert.getWidth == numberOfOutputs,
"non-zero inverter mask must have the same width as the output part of specified PLA table"
)
@@ -99,28 +100,28 @@ object pla {
// the OR matrix
val orMatrixOutputs: UInt = Cat(
- Seq
- .tabulate(numberOfOutputs) { i =>
- val andMatrixLines = table
- // OR matrix composed by input terms which makes this output bit a `1`
- .filter {
- case (_, or) => or.mask.testBit(i) && or.value.testBit(i)
- }.map {
- case (inputTerm, _) =>
- andMatrixOutputs(inputTerm.toString)
- }
- if (andMatrixLines.isEmpty) false.B
- else Cat(andMatrixLines).orR()
- }
- .reverse
- )
+ Seq
+ .tabulate(numberOfOutputs) { i =>
+ val andMatrixLines = table
+ // OR matrix composed by input terms which makes this output bit a `1`
+ .filter {
+ case (_, or) => or.mask.testBit(i) && or.value.testBit(i)
+ }.map {
+ case (inputTerm, _) =>
+ andMatrixOutputs(inputTerm.toString)
+ }
+ if (andMatrixLines.isEmpty) false.B
+ else Cat(andMatrixLines).orR()
+ }
+ .reverse
+ )
// the INV matrix, useful for decoders
val invMatrixOutputs: UInt = Cat(
Seq
.tabulate(numberOfOutputs) { i =>
if (inverterMask.testBit(i)) ~orMatrixOutputs(i)
- else orMatrixOutputs(i)
+ else orMatrixOutputs(i)
}
.reverse
)