Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 9 insertions, 8 deletions

diff --git a/src/main/scala/chisel3/util/experimental/group.scala b/src/main/scala/chisel3/util/experimental/group.scala
index e43115d0..202c95d8 100644
--- a/src/main/scala/chisel3/util/experimental/group.scala
+++ b/src/main/scala/chisel3/util/experimental/group.scala
@@ -3,7 +3,7 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
+import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.internal.requireIsHardware
 import firrtl.Transform
 import firrtl.transforms.{GroupAnnotation, GroupComponents}
@@ -46,12 +46,14 @@ object group {
     * @tparam T Parent type of input components
     */
   def apply[T <: Data](
-      components: Seq[T],
-      newModule: String,
-      newInstance: String,
-      outputSuffix: Option[String] = None,
-      inputSuffix: Option[String] = None
-  )(implicit compileOptions: CompileOptions): Unit = {
+    components:   Seq[T],
+    newModule:    String,
+    newInstance:  String,
+    outputSuffix: Option[String] = None,
+    inputSuffix:  Option[String] = None
+  )(
+    implicit compileOptions: CompileOptions
+  ): Unit = {
     if (compileOptions.checkSynthesizable) {
       components.foreach { data =>
         requireIsHardware(data, s"Component ${data.toString} is marked to group, but is not bound.")
@@ -64,4 +66,3 @@ object group {
     })
   }
 }
-