diff options
| author | ducky | 2016-11-17 13:01:03 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:31:12 -0800 |
| commit | 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch) | |
| tree | 7f6f9de04de6eb08878ac46be339fefc2a71395f /src/main/scala/chisel3/util/Reg.scala | |
| parent | cd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff) | |
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/main/scala/chisel3/util/Reg.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index f41d789c..00005e3a 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -53,7 +53,7 @@ object ShiftRegister * @param n number of cycles to delay * @param en enable the shift */ - def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = { + def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = { // The order of tests reflects the expected use cases. if (n != 0) { RegEnable(apply(in, n-1, en), en) |