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| author | Jim Lawson | 2016-08-18 12:35:34 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-18 12:35:34 -0700 |
| commit | d18274e307271809db2c27676f1dca40a49c9627 (patch) | |
| tree | 2632a0e409bea3f9069c5ebfb555cc1ec04caa4f /src/main/scala/chisel3/util/Reg.scala | |
| parent | ddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff) | |
| parent | 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f (diff) | |
Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests
Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
Diffstat (limited to 'src/main/scala/chisel3/util/Reg.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 81de4754..37c28b14 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -25,7 +25,8 @@ object RegInit { object RegEnable { def apply[T <: Data](updateData: T, enable: Bool): T = { - val r = Reg(updateData) + val clonedUpdateData = updateData.chiselCloneType + val r = Reg(clonedUpdateData) when (enable) { r := updateData } r } |