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authorJack Koenig2022-01-10 16:32:51 -0800
committerGitHub2022-01-10 16:32:51 -0800
commit2b48fd15a7711dcd44334fbbc538667a102a581a (patch)
tree4b4766347c3943d65c13e5de2d139b14821eec61 /src/main/scala/chisel3/util/OneHot.scala
parent92e77a97af986629766ac9038f0ebc8ab9a48fa1 (diff)
parentbff8dc0738adafa1176f6959a33ad86f6373c558 (diff)
Merge pull request #2246 from chipsalliance/scalafmt
Add scalafmt configuration and apply it.
Diffstat (limited to 'src/main/scala/chisel3/util/OneHot.scala')
-rw-r--r--src/main/scala/chisel3/util/OneHot.scala11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 03f470c7..23b350e5 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -20,15 +20,15 @@ import chisel3._
object OHToUInt {
def apply(in: Seq[Bool]): UInt = apply(Cat(in.reverse), in.size)
def apply(in: Vec[Bool]): UInt = apply(in.asUInt, in.size)
- def apply(in: Bits): UInt = apply(in, in.getWidth)
+ def apply(in: Bits): UInt = apply(in, in.getWidth)
def apply(in: Bits, width: Int): UInt = {
if (width <= 2) {
Log2(in, width)
} else {
- val mid = 1 << (log2Ceil(width)-1)
- val hi = in(width-1, mid)
- val lo = in(mid-1, 0)
+ val mid = 1 << (log2Ceil(width) - 1)
+ val hi = in(width - 1, mid)
+ val lo = in(mid - 1, 0)
Cat(hi.orR, apply(hi | lo, mid))
}
}
@@ -44,7 +44,7 @@ object OHToUInt {
*/
object PriorityEncoder {
def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(_.asUInt))
- def apply(in: Bits): UInt = apply(in.asBools)
+ def apply(in: Bits): UInt = apply(in.asBools)
}
/** Returns the one hot encoding of the input UInt.
@@ -52,7 +52,6 @@ object PriorityEncoder {
* @example {{{
* UIntToOH(2.U) // results in "b0100".U
* }}}
- *
*/
object UIntToOH {
def apply(in: UInt): UInt = 1.U << in