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authorJack Koenig2022-01-10 16:32:51 -0800
committerGitHub2022-01-10 16:32:51 -0800
commit2b48fd15a7711dcd44334fbbc538667a102a581a (patch)
tree4b4766347c3943d65c13e5de2d139b14821eec61 /src/main/scala/chisel3/util/MixedVec.scala
parent92e77a97af986629766ac9038f0ebc8ab9a48fa1 (diff)
parentbff8dc0738adafa1176f6959a33ad86f6373c558 (diff)
Merge pull request #2246 from chipsalliance/scalafmt
Add scalafmt configuration and apply it.
Diffstat (limited to 'src/main/scala/chisel3/util/MixedVec.scala')
-rw-r--r--src/main/scala/chisel3/util/MixedVec.scala4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index 14d6be38..5f8c9da8 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -19,6 +19,7 @@ import scala.collection.immutable.ListMap
* }}}
*/
object MixedVecInit {
+
/**
* Create a MixedVec wire from a Seq of values.
*/
@@ -45,6 +46,7 @@ object MixedVecInit {
* @return MixedVec with the given types.
*/
object MixedVec {
+
/**
* Create a MixedVec type from a Seq of Chisel types.
*/
@@ -111,7 +113,7 @@ final class MixedVec[T <: Data](private val eltsIn: Seq[T]) extends Record with
*/
def :=(that: Seq[T]): Unit = {
require(this.length == that.length)
- for ((a, b) <- this zip that)
+ for ((a, b) <- this.zip(that))
a := b
}