diff options
| author | Jim Lawson | 2016-12-12 09:14:33 -0800 |
|---|---|---|
| committer | GitHub | 2016-12-12 09:14:33 -0800 |
| commit | b581a24728bfba0c39ed2c032fd86f628a1e1a50 (patch) | |
| tree | f625219f936d39e760192aa69df17e776b95dd56 /src/main/scala/chisel3/util/LFSR.scala | |
| parent | 0bd9ae059368570dc72f25f7939afa5cfe5fd06e (diff) | |
| parent | ad53161bbb9f67e16b88ca7a508a537f88d77e05 (diff) | |
Merge branch 'master' into buildinfousepackageaspath
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index fedbf194..83dc907d 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -15,9 +15,9 @@ object LFSR16 { * * @param increment optional control to gate when the LFSR updates. */ - def apply(increment: Bool = Bool(true)): UInt = { + def apply(increment: Bool = true.B): UInt = { val width = 16 - val lfsr = Reg(init=UInt(1, width)) + val lfsr = Reg(init=1.U(width.W)) when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } lfsr } |
