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authorJim Lawson2016-07-19 13:43:48 -0700
committerJim Lawson2016-07-19 13:43:48 -0700
commitb27f29902d9f1d886e8edf1fc5e960cf9a634184 (patch)
treec6f3e27e46e5ed9c3cc62f2c368c766cdded74c6 /src/main/scala/chisel3/util/LFSR.scala
parent083610b2faa456dfccc4365dd115565d36e522fa (diff)
parent12810b5efe6a8f872fbc1c63cdfb835ca354624f (diff)
Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
new file mode 100644
index 00000000..a30c276f
--- /dev/null
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+/** LFSRs in all shapes and sizes.
+ */
+
+package chisel3.util
+
+import chisel3._
+
+// scalastyle:off magic.number
+/** linear feedback shift register
+ */
+object LFSR16
+{
+ def apply(increment: Bool = Bool(true)): UInt =
+ {
+ val width = 16
+ val lfsr = Reg(init=UInt(1, width))
+ when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
+ lfsr
+ }
+}
+// scalastyle:on magic.number
+