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authorRichard Lin2017-03-08 17:38:14 -0800
committerGitHub2017-03-08 17:38:14 -0800
commita290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch)
tree3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/main/scala/chisel3/util/LFSR.scala
parent09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff)
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
-rw-r--r--src/main/scala/chisel3/util/LFSR.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index 94c340c4..ff2bf840 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -19,7 +19,7 @@ object LFSR16 {
@chiselName
def apply(increment: Bool = true.B): UInt = {
val width = 16
- val lfsr = Reg(init=1.U(width.W))
+ val lfsr = RegInit(1.U(width.W))
when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
lfsr
}