diff options
| author | ducky | 2016-11-17 13:01:03 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:31:12 -0800 |
| commit | 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 (patch) | |
| tree | 7f6f9de04de6eb08878ac46be339fefc2a71395f /src/main/scala/chisel3/util/LFSR.scala | |
| parent | cd904da0aa0e96ba679906a3ee5dbdc068eace48 (diff) | |
Restyle a lot of test code, mainly with regex
Diffstat (limited to 'src/main/scala/chisel3/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/LFSR.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala index fedbf194..83dc907d 100644 --- a/src/main/scala/chisel3/util/LFSR.scala +++ b/src/main/scala/chisel3/util/LFSR.scala @@ -15,9 +15,9 @@ object LFSR16 { * * @param increment optional control to gate when the LFSR updates. */ - def apply(increment: Bool = Bool(true)): UInt = { + def apply(increment: Bool = true.B): UInt = { val width = 16 - val lfsr = Reg(init=UInt(1, width)) + val lfsr = Reg(init=1.U(width.W)) when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } lfsr } |
