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authorgrebe2016-12-15 01:47:26 -0500
committerGitHub2016-12-15 01:47:26 -0500
commitd622b43bd03b8f17fe9a11d41d8dd0865989c0c5 (patch)
tree09c58614b14d0e7fc7ca752ff17d1bbd6a39ebb9 /src/main/scala/chisel3/util/Decoupled.scala
parentf9d528b3763429275430b84839ccf0b4570531a2 (diff)
parent59a7c25d5c708305216532ec49c8120e59219f69 (diff)
Merge branch 'master' into fixedPointFromBits
Diffstat (limited to 'src/main/scala/chisel3/util/Decoupled.scala')
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index fcda6943..4a97724a 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -37,12 +37,13 @@ object ReadyValidIO {
dat
}
- /** Indicate no enqueue occurs. Valid is set to false, and all bits are set to zero.
+ /** Indicate no enqueue occurs. Valid is set to false, and bits are
+ * connected to an uninitialized wire
*/
def noenq(): Unit = {
target.valid := false.B
// We want the type from the following, not any existing binding.
- target.bits := target.bits.cloneType.fromBits(0.asUInt)
+ target.bits := Wire(target.bits.cloneType)
}
/** Assert ready on this port and return the associated data bits.