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authorJack2022-07-30 22:41:15 +0000
committerJack2022-07-30 22:41:15 +0000
commit4cd44fa4dab370fcc5c20bcacc1fa0ee02327252 (patch)
tree05730be260feca0d2a870c4bb88325d36631a8fc /src/main/scala/chisel3/util/CircuitMath.scala
parentfe9635ef21bad233945617a24ab16cfa4055f2d1 (diff)
parentbced77045c8fc5db37e40b159c49220929e15d46 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'src/main/scala/chisel3/util/CircuitMath.scala')
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index df60f059..9e4890a9 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,7 +6,6 @@
package chisel3.util
import chisel3._
-import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
/** Returns the base-2 integer logarithm of an UInt.
*
@@ -22,7 +21,6 @@ object Log2 {
/** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
*/
- @chiselName
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
0.U