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authorJim Lawson2016-07-27 10:36:55 -0700
committerJim Lawson2016-07-27 10:36:55 -0700
commit138329479914ac37b49a5a44841dc1de2929dca5 (patch)
tree0b539d74e3176853fe384a38cfc9a1dfa5e2bf31 /src/main/scala/chisel3/package.scala
parent089987c3e0b2bc390935a4d9d44db38a18c47901 (diff)
More compatibility fixes
Diffstat (limited to 'src/main/scala/chisel3/package.scala')
-rw-r--r--src/main/scala/chisel3/package.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 5fcf5e67..a0264df4 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -7,7 +7,7 @@ package object chisel3 {
import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
import util.BitPat
- import chisel3.core.{Binding, Bits, Element, FlippedBinder}
+ import chisel3.core.{Binding, FlippedBinder}
import chisel3.util._
import chisel3.internal.firrtl.Port
@@ -120,6 +120,7 @@ package object chisel3 {
val NODIR = chisel3.core.Direction.Unspecified
type ChiselException = chisel3.internal.ChiselException
type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+ val ValidIO = chisel3.util.Valid
val Decoupled = chisel3.util.DecoupledIO
class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {