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| author | Richard Lin | 2019-01-21 16:24:43 -0800 |
|---|---|---|
| committer | GitHub | 2019-01-21 16:24:43 -0800 |
| commit | 9e992816e570284193e121cd9c24503fd8cb4427 (patch) | |
| tree | 90205ab0c936d50f4853bb7dc6293a4b62d47edf /src/main/scala/chisel3/package.scala | |
| parent | 3b3405e8bd496749dcb47e17156c0224a6f8a496 (diff) | |
Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994)
Diffstat (limited to 'src/main/scala/chisel3/package.scala')
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index e79a1186..3b1275f6 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -430,8 +430,8 @@ package object chisel3 { // scalastyle:ignore package.object.name val dontTouch = chisel3.core.dontTouch type BaseModule = chisel3.core.BaseModule - type MultiIOModule = chisel3.core.ImplicitModule - type RawModule = chisel3.core.UserModule + type RawModule = chisel3.core.RawModule + type MultiIOModule = chisel3.core.MultiIOModule type ExtModule = chisel3.core.ExtModule val IO = chisel3.core.IO |